1. Field of the Invention
The present invention relates to a method of forming a contact hole, and more particularly, to a method of forming a node contact hole on a semiconductor wafer.
2. Description of the Prior Art
A memory cell of dynamic random access memory (DRAM) comprises a transistor and a capacitor that is stacked on the transistor. The transistor is used as a switch for controlling a bit line and reading the data stored in the capacitor. The electrical connection between the transistor and the bottom electrode of the capacitor is a conductor-filled node contact hole. Generally, a self-alignment contact (SAC) process is performed to form the node contact hole, which accurately defines the position of the node contact hole through the area between two bit lines.
Please refer to FIG. 1, FIG. 2A and FIG. 2B. FIG. 1 is an overhead schematic diagram of a semiconductor wafer 10 according to the prior art. FIG. 2A is a cross-sectional schematic diagram along line a--a of the semiconductor wafer 10 shown in FIG. 1. FIG. 2B is a cross-sectional schematic diagram along line b--b of the semiconductor wafer 10 shown in FIG. 1. A semiconductor wafer 10 comprises a silicon substrate 12, a plurality of approximately square cross-sectional word lines 14 positioned on the silicon substrate 12, a bottom dielectric layer 20 positioned on each word line 14, a first dielectric layer 22 positioned on the bottom dielectric layer 20, two bit lines 24 positioned on two predetermined areas of the first dielectric layer 22, and a second dielectric layer 28 covering the first dielectric layer 22 and the two bit lines 24. The vertical faces of each word line 14 are covered by a first spacer 16. The vertical faces of each bit line 24 are covered by a second spacer 26. The semiconductor wafer 10 further comprises a landing pad 18 that protrudes from the silicon substrate 12 and is inlaid between two adjacent first spacers 16.
Please refer to FIG. 3, FIG. 4A and FIG. 4B. FIG. 3 is an overhead schematic diagram of a photoresist layer 30 formed on the semiconductor wafer 10 shown in FIG. 1 during a node contact hole process using a self-alignment contact technique. FIG. 4A is a cross-sectional schematic diagram along line c--c of the semiconductor wafer 10 shown in FIG. 3. FIG. 4B is a cross-sectional schematic diagram along line d--d of the semiconductor wafer 10 shown in FIG. 3. During a node contact hole process using a self-alignment contact technique, a lithographic process is first performed to form a photoresist layer 30 on the semiconductor wafer 10 wherein the photoresist layer 30 comprises at least one opening 32 to the second dielectric layer 28 to define the position of the node contact hole. The opening 32 is positioned between the two adjacent second spacers 26 and the two adjacent first spacers 16. Consequently, the photoresist layer 30 for a DRAM would have a plurality of openings 32 arranged as a matrix.
Please refer to FIG. 5A and FIG. 5B. FIG. 5A is a cross-sectional schematic diagram of a node contact hole 34 formed on the semiconductor wafer 10 shown in FIG. 4A. FIG. 5B is a cross-sectional schematic diagram of a node contact hole 34 formed on the semiconductor wafer 10 shown in FIG. 4B. After the photoresist layer 30 is completed, an anisotropic dry etching process is performed. In a condition that the first spacers 16 and the second spacers 26 can't be removed, the second dielectric layer 28 and the first dielectric layer 22 under the opening 32 of the photoresist layer 30 are vertically removed so as to form a node contact hole 34. Finally, the photoresist layer 30 is removed to complete the node contact hole process.
Please refer to FIG. 6A and FIG. 6B. FIG. 6A is a cross-sectional diagram of a bottom electrode of a capacitor formed within the node contact hole 34 shown in FIG. 5A. FIG. 6B is a cross-sectional diagram of a bottom electrode of a capacitor formed within the node contact hole 34 shown in FIG. 5B. After the node contact hole 34 is completed, a bottom electrode of a capacitor can be formed within the node contact hole 34. First, a polysilicon layer 36 is formed on the semiconductor wafer 10 that fills the node contact hole 34. Then, the polysilicon layer 36 positioned outside a predetermined area is removed which leaves the remaining polysilicon layer 36 inlaid with the node contact hole 34. The bottom of the remaining polysilicon layer 36 is in contact with the landing pad 18 to electrically connect to the transistor of the semiconductor wafer 10. The top of the remaining polysilicon layer 36 protruding from the second dielectric layer 28 is used as the bottom electrode of the capacitor.
The position of the node contact hole 34 is defined by using a self-alignment technique along the opening 32 of the photoresist layer 30. Hence, the parameters of the lithographic process must be carefully controlled to ensure the accuracy of the position of the opening 32, thereby ensuring the accuracy of the position of the node contact hole 34.
As the pattern of the DRAM shrinks, the distance between two adjacent node contact holes 34 becomes shorter. Consequently, the openings 32 of the photoresist layer 30 must be formed closer to each other. However, when an exposure process is performed on this smaller pattern during the lithographic process, the resolution of the pattern is reduced because of the difficulty in controlling the exposure energy and focus length for the matrix arrangement of openings 32. The lowered resolution will decrease the accuracy in defining the position of the opening 32 and bring about many adverse influences on the properties of the subsequently formed node contact hole 34.